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cmos dram K4F660811B,k4f640811b this is a family of 8,388,608 x 8 bit fast page mode cmos drams. fast page mode offers high speed random access of memory cells within the same row. refresh cycle(4k ref. or 8k ref.), access time (-45, -50 or -60), package type (soj or tsop-ii) are optiona l fea- tures of this family. all of this family have cas -before- ras refresh, ras -only refresh and hidden refresh capabilities. this 8mx8 fast page mode dram family is fabricated using samsung s advanced cmos process to realize high band-width, low power consumption and high reliability. ? fast page mode operation ? cas -before- ras refresh capability ? ras -only and hidden refresh capability ? fast parallel test mode capability ? ttl(5.0v) compatible inputs and outputs ? early write or output enable controlled write ? jedec standard pinout ? available in plastic soj and tsop(ii) packages ? +5.0v 10% power supply control clocks ras cas w vcc vss a0~a12 (a0~a11)*1 a0~a9 (a0~a10)*1 memory array 8,388,608 x 8 cells samsung electronics co., ltd. reserves the right to change products and specifications without notice. 8m x 8bit cmos dynamic ram with fast page mode description functional block diagram note) *1 : 4k refresh s e n s e a m p s & i / o dq0 to dq7 data out buffer data in buffer row decoder column decoder vbb generator refresh timer refresh control refresh counter row address buffer col. address buffer oe ? part identification - K4F660811B-jc(5.0v, 8k ref.) - k4f640811b-jc(5.0v, 4k ref.) - K4F660811B-tc(5.0v, 8k ref.) - k4f640811b-tc(5.0v, 4k ref.) features ? refresh cycles part no. refresh cycle refresh time normal K4F660811B* 8k 64ms k4f640811b 4k ? performance range speed t rac t cac t rc t pc -45 45ns 12ns 80ns 31ns -50 50ns 13ns 90ns 35ns -60 60ns 15ns 110ns 40ns ? active power dissipation speed 8k 4k -45 550 715 -50 495 660 -60 440 605 unit : mw * access mode & ras only refresh mode : 8k cycle/64ms cas -before- ras & hidden refresh mode : 4k cycle/64ms
cmos dram K4F660811B,k4f640811b v cc dq0 dq1 dq2 dq3 n.c v cc w ras a0 a1 a2 a3 a4 a5 v cc v ss dq7 dq6 dq5 dq4 v ss cas oe a12(n.c)* a11 a10 a9 a8 a7 a6 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 pin configuration (top views) * (n.c) : n.c for 4k refresh product pin name pin function a0 - a12 address inputs(8k product) a0 - a11 address inputs(4k product) dq0 - 7 data in/out v ss ground ras row address strobe cas column address strobe w read/write input oe data output enable v cc power(+5.0v) n.c no connection v cc dq0 dq1 dq2 dq3 n.c v cc w ras a0 a1 a2 a3 a4 a5 v cc v ss dq7 dq6 dq5 dq4 v ss cas oe a12(n.c)* a11 a10 a9 a8 a7 a6 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 (t : 400mil tsop(ii)) (j : 400mil soj) ? K4F660811B-j ? k4f640811b-j ? K4F660811B-t ? k4f640811b-t
cmos dram K4F660811B,k4f640811b absolute maximum ratings * permanent device damage may occur if "absolute maximum ratings" are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for ex tended periods may affect device reliability. parameter symbol rating units voltage on any pin relative to v ss v in, v out -1.0 to +7.0 v voltage on v cc supply relative to v ss v cc -1.0 to +7.0 v storage temperature tstg -55 to +150 c power dissipation p d 1 w short circuit output current i os address 50 ma recommended operating conditions (voltage referenced to vss, t a = 0 to 70 c) *1 : v cc +2.0v at pulse width 20ns which is measured at v cc *2 : -2.0 at pulse width 20ns which is measured at v ss parameter symbol min typ max units supply voltage v cc 4.5 5.0 5.5 v ground v ss 0 0 0 v input high voltage v ih 2.4 - v cc +1.0 *1 v input low voltage v il -1.0 *2 - 0.8 v dc and operating characteristics (recommended operating conditions unless otherwise noted.) parameter symbol min max units input leakage current (any input 0 v in v cc +0.5v, all other pins not under test=0 volt) i i(l) -5 5 ua output leakage current (data out is disabled, 0v v out v cc ) i o(l) -5 5 ua output high voltage level(i oh =-5ma) v oh 2.4 - v output low voltage level(i ol =4.2ma) v ol - 0.4 v
cmos dram K4F660811B,k4f640811b *note : i cc1 , i cc3 , i cc4 and i cc6 are dependent on output loading and cycle rates. specified values are obtained with the output open. i cc is specified as an average current. in i cc1 , i cc3 and i cc6, address can be changed maximum once while ras =v il . in i cc4 , address can be changed maximum once within one fast page mode cycle time, t pc . dc and operating characteristics (continued) i cc1 * : operating current ( ras and cas , address cycling @ t rc =min.) i cc2 : standby current ( ras = cas = w =v ih ) i cc3 * : ras -only refresh current ( cas =v ih , ras , address cycling @ t rc =min.) i cc4 * : fast page mode current ( ras =v il , cas , address cycling @ t pc =min.) i cc5 : standby current ( ras = cas = w =v cc -0.2v) i cc6 * : cas -before- ras refresh current ( ras and cas cycling @ t rc =min) symbol power speed max units K4F660811B k4f640811b i cc1 don t care -45 -50 -60 100 90 80 130 120 110 ma ma ma i cc2 normal don t care 2 2 ma i cc3 don t care -45 -50 -60 100 90 80 130 120 110 ma ma ma i cc4 don t care -45 -50 -60 70 60 50 80 70 60 ma ma ma i cc5 normal don t care 1 1 ma i cc6 don t care -45 -50 -60 100 90 80 130 120 110 ma ma ma
cmos dram K4F660811B,k4f640811b capacitance (t a =25 c, v cc =5.0v, f=1mhz) parameter symbol min max units input capacitance [a0 ~ a12] c in1 - 5 pf input capacitance [ ras , cas , w , oe ] c in2 - 7 pf output capacitance [dq0 - dq7] c dq - 7 pf test condition : v cc =5.0v 10%, vih/vil=2.4/0.8v, voh/vol=2.4/0.4v parameter symbol -45 -50 -60 units note min max min max min max random read or write cycle time t rc 80 90 110 ns read-modify-write cycle time t rwc 115 133 153 ns access time from ras t rac 45 50 60 ns 3,4,10 access time from cas t cac 12 13 15 ns 3,4,5 access time from column address t aa 23 25 30 ns 3,10 cas to output in low-z t clz 0 0 0 ns 3 output buffer turn-off delay t off 0 13 0 13 0 13 ns 6 transition time (rise and fall) t t 1 50 1 50 1 50 ns 2 ras precharge time t rp 25 30 40 ns ras pulse width t ras 45 10k 50 10k 60 10k ns ras hold time t rsh 12 13 15 ns cas hold time t csh 45 50 60 ns cas pulse width t cas 12 10k 13 10k 15 10k ns ras to cas delay time t rcd 18 33 20 37 20 45 ns 4 ras to column address delay time t rad 13 22 15 25 15 30 ns 10 cas to ras precharge time t crp 5 5 5 ns row address set-up time t asr 0 0 0 ns row address hold time t rah 8 10 10 ns column address set-up time t asc 0 0 0 ns column address hold time t cah 8 10 10 ns column address to ras lead time t ral 23 25 30 ns read command set-up time t rcs 0 0 0 ns read command hold time referenced to cas t rch 0 0 0 ns 8 read command hold time referenced to ras t rrh 0 0 0 ns 8 write command hold time t wch 8 10 10 ns write command pulse width t wp 8 10 10 ns write command to ras lead time t rwl 13 15 15 ns write command to cas lead time t cwl 12 13 15 ns data set-up time t ds 0 0 0 ns 9 data hold time t dh 10 10 10 ns 9 ac characteristics (0 c t a 70 c, see note 1,2)
cmos dram K4F660811B,k4f640811b ac characteristics (continued) parameter symbol -45 -50 -60 units note min max min max min max refresh period (4k, normal) t ref 64 64 64 ms refresh period (8k, normal) t ref 64 64 64 ms write command set-up time t wcs 0 0 0 ns 7 cas to w delay time t cwd 32 36 38 ns 7 ras to w delay time t rwd 67 73 83 ns 7 column address to w delay time t awd 43 48 53 ns 7 cas precharge w delay time t cpwd 48 53 60 ns cas set-up time ( cas -before- ras refresh) t csr 5 5 5 ns cas hold time ( cas -before- ras refresh) t chr 10 5 5 ns ras to cas precharge time t rpc 5 5 5 ns access time from cas precharge t cpa 26 30 35 ns 3 fast page mode cycle time t pc 31 35 40 ns fast page mode read-modify-write cycle time t prwc 70 76 85 ns cas precharge time (fast page cycle) t cp 9 10 10 ns ras pulse width (fast page cycle) t rasp 45 200k 50 200k 60 200k ns ras hold time from cas precharge t rhcp 28 30 35 ns oe access time t oea 12 13 15 ns oe to data delay t oed 12 13 13 ns output buffer turn off delay time from oe t oez 0 13 0 13 0 13 ns 6 oe command hold time t oeh 12 13 15 ns write command set-up time (test mode in) t wts 10 10 10 ns 11 write command hold time (test mode in) t wth 15 15 15 ns 11 w to ras precharge time ( c -b- r refresh) t wrp 10 10 10 ns w to ras hold time ( c -b- r refresh) t wrh 10 10 10 ns ras pulse width ( c -b- r self refresh) t rass 100 100 100 us 13,14,15 ras precharge time ( c -b- r self refresh) t rps 80 90 110 ns 13,14,15 cas hold time ( c -b- r self refresh) t chs -50 -50 -50 ns 13,14,15
cmos dram K4F660811B,k4f640811b test mode cycle parameter symbol -45 -50 -60 units note min max min max min max random read or write cycle time t rc 85 95 115 ns read-modify-write cycle time t rwc 120 138 160 ns access time from ras t rac 50 55 65 ns 3,4,10,12 access time from cas t cac 17 18 20 ns 3,4,5,12 access time from column address t aa 28 30 35 ns 3,10,12 ras pulse width t ras 50 10k 55 10k 65 10k ns cas pulse width t cas 17 10k 18 10k 20 10k ns ras hold time t rsh 17 18 20 ns cas hold time t csh 50 55 65 ns column address to ras lead time t ral 28 30 35 ns cas to w delay time t cwd 37 41 43 ns 7 ras to w delay time t rwd 72 78 88 ns 7 column address to w delay time t awd 48 53 58 ns 7 fast page mode cycle time t pc 36 40 45 ns fast page mode read-modify-write cycle time t prwc 75 81 90 ns ras pulse width (fast page cycle) t rasp 50 200k 55 200k 65 200k ns access time from cas precharge t cpa 31 35 40 ns 3 oe access time t oea 17 18 20 ns oe to data delay t oed 17 18 18 ns oe command hold time t oeh 17 18 20 ns ( note 11 )
cmos dram K4F660811B,k4f640811b notes an initial pause of 200us is required after power-up followed by any 8 ras -only refresh or cas -before- ras refresh cycles before proper device operation is achieved. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih (min) and v il (max) and are assumed to be 5ns for all inputs. measured with a load equivalent to 2 ttl load and 100pf. operation within the t rcd (max) limit insures that t rac (max) can be met. t rcd (max) is specified as a reference point only. if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . assumes that t rcd 3 t rcd (max). t off (min)and t oez (max) define the time at which the output achieves the open circuit condition and are not referenced v oh or v ol . t wcs , t rwd , t cwd and t awd are non restrictive operating parameters. they are included in the data sheet as electrical char- acteristics only. if t wcs 3 t wcs (min), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. if t cwd 3 t cwd (min), t rwd 3 t rwd (min) and t awd 3 t awd (min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. if neither of the above conditions is satisfied, the condition of the data out is indeterminate. either t rch or t rrh must be satisfied for a read cycle. these parameters are referenced to cas falling edge in early write cycles and to w falling edge in read-modify-write cycles. operation within the t rad (max) limit insures that t rac (max) can be met. t rad (max) is specified as a reference point only. if t rad is greater than the specified t rad (max) limit, then access time is controlled by t aa . these specifications are applied in the test mode. in test mode read cycle, the value of t rac , t aa , t cac is delayed by 2ns to 5ns for the specified values. these parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. if t rass 3 100us, then ras precharge time must use t rps instead of t rp . for ras -only refresh and burst cas -before- ras refresh mode, 4096(4k/8k) cycles of burst refresh must be executed within 64ms before and after self refresh, in order to meet refresh specification. for distributed cas -before- ras with 15.6us interval cas -before- ras refresh should be executed with in 15.6us immedi- ately before and after self refresh in order to meet refresh specification. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 1. 2. 3. 4. 15.
cmos dram K4F660811B,k4f640811b t crp ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v oh - v ol - dq0 ~ dq3(7) read cycle column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t aa t oea t cac t clz t rac open data-out t oez t rrh t rch don t care undefined t rcs t off
cmos dram K4F660811B,k4f640811b t wcs write cycle ( early write ) note : d out = open ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dq0 ~ dq3(7) column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t crp t wp t ds t dh t wch t cwl t rwl don t care data-in undefined
cmos dram K4F660811B,k4f640811b t oed ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dq0 ~ dq3(7) column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t crp data-in t wp don t care write cycle ( oe controlled write ) note : d out = open t cwl t rwl t ds t dh t oeh undefined
cmos dram K4F660811B,k4f640811b ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v i/oh - v i/ol - dq0 ~ dq3(7) row addr t ras t rwc t rp t rsh t rcd t cas t csh t rad t asr t rah t asc t cah t crp valid t wp don t care read - modify - wrtie cycle t rwl t cwl t oez t oea t oed t awd t cwd t rwd data-out undefined valid data-in t rac t aa t cac t clz t ds t dh column address
cmos dram K4F660811B,k4f640811b t rch t oez t clz ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v oh - v ol - dq0 ~ dq3(7) column address row addr t rhcp t rasp t cas t asc t rad t asr t rah t asc t cah t crp valid don t care fast page read cycle t oez t rrh data-out undefined valid data-out column address column address t rsh t cas t rcd t pc ? t csh t cah t asc t cah ? ? ? t rch ? t rcs t rcs t rcs t oea t cac t oea t cac t oea t cac valid data-out t clz t off t aa t off t aa t clz t off t oez t rac t aa ? ? t cp t cas t rp t cp t ral
cmos dram K4F660811B,k4f640811b t asc t cah ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dq0 ~ dq3(7) column address row addr t rhcp t rasp t cas t rad t asr t rah t asc t crp valid don t care fast page write cycle ( early write ) data-in undefined valid data-in t ds note : d out = open column address column address t rsh t cas t rcd t pc ? t csh t cah t cah ? ? ? t wcs t wch t wcs valid data-in ? ? t wp t cwl t wp t wch t wp t wcs t wch t cwl t rwl t cwl t dh t ds t dh t ds t dh ? ? ? t rp t cp t cp t cas t pc t ral t asc
cmos dram K4F660811B,k4f640811b t cac t asc t asc ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v i/oh - v i/ol - dq0 ~ dq3(7) row addr t csh t rasp t asr valid don t care fast page read - modify - write cycle data-out undefined t rcd t cp t rad t cah t wp t dh col. addr col. addr t cas t cas t crp t cah t ral t prwc t rcs t cwl t cwd t awd t rwd t wp t cwd t awd t cwl t aa t rac t oea t clz t cac t oez t cpwd t oed valid data-in valid data-out valid data-in t clz t ds t oea t aa t dh t ds t oez t oed t rwl t rp t rsh t rah
cmos dram K4F660811B,k4f640811b ras v ih - v il - cas v ih - v il - a v ih - v il - row addr t ras t rc t rp t asr t rah t crp don t care ras - only refresh cycle undefined note : w , oe , d in = don t care d out = open t rpc t crp cas - before - ras refresh cycle note : oe , a = don t care ras v ih - v il - cas v ih - v il - t ras t rc t rp t wrp t rpc t rp t cp t chr t csr w v ih - v il - t wrh t off t rpc v oh - v ol - dq0 ~ dq3(7) open
cmos dram K4F660811B,k4f640811b t wrh t off ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v oh - v ol - dq0 ~ dq3(7) hidden refresh cycle ( read ) column address row address t ras t rc t chr t rcd t rad t asr t rah t asc t cah t crp t rcs t aa t oea t cac t clz t rac open don t care t rsh t oez undefined t rc data-out t rp t rp t ras t ral
cmos dram K4F660811B,k4f640811b ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dq0 ~ dq3(7) hidden refresh cycle ( write ) column address row address t ras t rc t chr t rcd t rad t asr t rah t asc t cah t crp don t care t rsh data-in t wrp t wrh undefined t rc note : d out = open t wch t wp t dh t rp t rp t ras t ds t wcs t ral
cmos dram K4F660811B,k4f640811b don t care undefined cas - before - ras self refresh cycle note : oe , a = don t care ras v ih - v il - cas v ih - v il - t rass t rps t rpc t wrp t chs t rp t cp t csr w v ih - v il - t wrh t off t rpc open v oh - v ol - dq0 ~ dq3(7) test mode in cycle note : oe , a = don t care ras v ih - v il - cas v ih - v il - t ras t rc t rp t rpc t wts t rpc t rp t cp t chr t csr w v ih - v il - t wth t off open v oh - v ol - dq0 ~ dq3(7)
cmos dram K4F660811B,k4f640811b 32 soj 400mil 0 . 4 0 0 ( 1 0 . 1 6 ) 0 . 4 3 5 ( 1 1 . 0 6 ) 0 . 4 4 5 ( 1 1 . 3 0 ) 0.830 (21.08) 0.820 (20.84) max 0.841 (21.36) m a x 0 . 1 4 8 ( 3 . 7 6 ) 0.032 (0.81) 0.026 (0.66) 0.021 (0.53) 0.015 (0.38) 0.027 (0.69) 0.012 (0.30) 0.006 (0.15) 0 . 3 6 0 ( 9 . 1 5 ) 0 . 3 8 0 ( 9 . 6 5 ) min #32 #1 0.0375 (0.95) 0.050 (1.27) units : inches (millimeters) package dimension 32 tsop(ii) 400mil 0 . 4 5 5 ( 1 1 . 5 6 ) 0 . 4 7 1 ( 1 1 . 9 6 ) 0.829 (21.05) 0.821 (20.85) max 0.841 (21.35) 0.037 (0.95) 0.050 (1.27) units : inches (millimeters) 0.047 (1.20) min 0.002 (0.05) 0.020 (0.50) 0.012 (0.30) max 0.010 (0.25) 0.004 (0.10) 0 . 4 0 0 ( 1 0 . 1 6 ) 0~8 0.030 (0.75) 0.018 (0.45) typ 0.010 (0.25) o

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